Synopsys Galaxy Design Platform Enhanced with SoCBIST Solution for Core-Based Designs

ARM-Synopsys Reference Methodology Delivers SoC Test Solution for Core-based Design Flows

"As the industry-leading semiconductor IP supplier, our customers look to us for improved solutions to their increasingly difficult IP core test integration challenges," said Pete Harrod, CPU design and test manager, ARM. "Synopsys and ARM have worked closely together to enable a core test reuse solution for the ARM1136JF-S(TM) core, which will significantly reduce our customers' test development costs. The ARM-Synopsys Reference Methodology supports this innovative and effective SoC test solution, and ARM will provide test reuse optimized cores, test data and CTL models to help our customers simplify their SoC test challenges. Designers throughout the industry will benefit from this new standards-based approach to test for core-based designs."

The integration and verification of test in complex multimillion-gate SoCs poses formidable challenges for designers today. Integrating the design-for-test (DFT) structures of IP cores at the SoC level is difficult and time-consuming, and automatic test pattern generation (ATPG) at the SoC level can expose test problems late in the design process, slowing time to production. Synopsys' SoC test automation solution addresses these challenges by automating the creation and integration of IP cores that are optimized for test reuse. First, DFT Compiler automatically synthesizes test reuse IP cores, and creates IEEE P1450.6 CTL test models for them. Next, TetraMAX(R) ATPG generates reusable test patterns for these cores with high fault coverage. Finally, Synopsys' SoCBIST product reads the CTL models of these cores and automatically integrates the cores into the overall SoC, reusing pre-supplied core test patterns referenced from the SoC-level pattern set. In this way, DFT Compiler, TetraMAX ATPG and SoCBIST work together to automate test reuse in IP core-based designs within the Synopsys implementation platform.

"ST designs SoCs for a wide range of applications -- from wireless devices to set-top-boxes and other consumer applications. To help manage the rapidly growing complexity of SoC test within our design flows, we require a standardized IP test methodology across all of our design groups," said Sylvain Kritter, HCMOS design platform director, STMicroelectronics' Central R&D. "We partnered with Synopsys to create a standards-based SoC test automation solution that would enable us to deploy a streamlined test methodology and enable our designers to achieve significant productivity gains. As an ARM partner, we are very happy to see this SoC test automation solution included in the ARM-Synopsys Reference Methodology. We believe this approach will provide ST with the fastest and most comprehensive approach to test implementation for our ARM-based designs."

"Agilent, Synopsys, and ST Micro are leading the industry in development of IEEE P1450.6 CTL-based links between the EDA and ATE environments. This standards-based solution provides automation of SoC design-to-test, and is expected to dramatically reduce the time needed to develop test programs, making an order of magnitude improvement in time to market possible," said Tom Newsom, vice president and general manager of Agilent's SOC Test Business Unit. "With this capability, we can offer great time-to-market value to our customers by taking core test data directly from the design environment and providing optimized test development for the 93000 SOC Series test platform. We are very happy to be working with Synopsys, ARM and ST Micro, leaders in their respective markets of EDA, semiconductor IP and semiconductor products, to leverage the emerging CTL standard to enable a superior customer solution."

"Synopsys' customers are challenged with reducing their cost of test while improving product quality and achieving faster time to market," said Antun Domic, senior vice president and general manager, Synopsys Nanometer Analysis and Test business unit. "Our DFT Compiler SoCBIST product addresses these challenges and integrates seamlessly within the Galaxy Design Platform. We have further extended the capabilities of our DFT Compiler SoCBIST to automate test reuse for our customers' IP core-based design flows, which we now offer with strong support from world-class companies such as ARM, ST Microelectronics and Agilent."

Pricing and Availability

SoCBIST is an add-on option to DFT Compiler, and is available with the March 2003 production release. Pricing for DFT Compiler SoCBIST begins at $175,000 US list for a one-year technology subscription license (TSL).

Synopsys Versatile Test Solutions

Synopsys offers a complete line of integrated products and services to meet the most demanding manufacturing test requirements. The company's award-winning design-for-test offering includes the advanced DFT Compiler and TetraMAX ATPG tools. An integral part of the Synopsys Galaxy(TM) Design Platform, DFT Compiler incorporates the latest generation of Synopsys' patented 1-Pass test synthesis technology and enables design teams to efficiently meet their DFT closure goals. TetraMAX complements scan-based test methodologies by providing industry-leading ATPG performance, capacity and ease of use. Complementing its test products, Synopsys offers comprehensive test services delivered by its world-class team of DFT experts.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS) is the world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and is located in more than 60 offices throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.

Forward Looking Statements

The second and fifth paragraphs of this press release contain forward-looking statements within the meaning of the safe harbor provisions of Section 21E of the Securities Exchange Act of 1934, including statements regarding the expected cost and performance benefits of the Synopsys core test reuse solution. These statements are based on Synopsys' current expectations and beliefs. Actual results could differ materially from the results implied by these statements as a result of a number of factors including customer difficulties integrating the solution with their own design, which could increase customer cost and time to market, as well other factors contained in Synopsys' Annual Report on Form 10-K for the year ended October 31, 2002, as amended.

Synopsys is a registered trademark and DFT Compiler is a trademark of Synopsys Inc.

ARM is a registered trademark of ARM Limited. ARM1136JF-S is a trademark of ARM Limited. "ARM" is used to represent ARM Holdings plc (LSE: ARM and Nasdaq: ARMHY); its operating company ARM Limited; and the regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; and ARM Consulting (Shanghai) Co.Ltd.

All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

CONTACT: Synopsys, Inc.
             Nancy Renzullo, 650/584-1669
             renzullo@synopsys.com
              or
             Edelman
             Sarah Seifert, 650/492-2776
             sarah.seifert@edelman.com